Using All Processor Cores While Being Confident about Timing
• Presentation
This presentation describes research to address the use of all processor cores while retaining confidence about timing.
Publisher
Software Engineering Institute
Topic or Tag
Abstract
In this project, we aim to develop a solution to overcome this obstacle. This is a difficult challenge, because timing is determined by many shared resources in the memory system (including cache, memory banks, memory bus) with complex arbitration mechanisms, some of which are undocumented. The goal of our research is to demonstrate multicore timing confidence.
Part of a Collection
CMU SEI Research Review 2019